1. Field of the Invention
The present invention is related to a nonvolatile semiconductor memory, and is particularly related to a multi-level NAND-structured flash memory.
2. Description of the Related Art
A flash memory changes the amount of electric charges stored in a floating gate electrode of a memory cell to vary its threshold value, and stores data. For example, “1” corresponds to the threshold value of the memory cell being negative, and “0” corresponds to the threshold value being positive (e.g., refer to Jpn. Pat. Appln. KOKAI Publication No. 10-177797).
Recently, in order to decrease the value per bit or to increase a storage capacity, so-called multi-level flash memories have been developed to store multiple bit data in one memory cell. When 2-bit data is stored in one memory cell, four threshold distributions of the memory cell exist in accordance with quaternary data.
(1) By the way, the flash memory has basic modes: write, erase and read (including verification reading. Hereinafter the same.). At the start of these modes, it is necessary to generate a high voltage (e.g., a write potential Vpgm, a transfer potential Vpass, an erase potential Vera), and charge a bit line.
Therefore, at the start of writing, erasing and reading, an amount of current consumption increases, and its peak value, that is, peak current value also increases.
However, if a high peak current is generated in the flash memory, an adverse effect can be exerted to a system including the flash memory.
For example, the peak current generated in the flash memory in a portable device such as a digital camera and mobile telephone causes a decrease in a value of a power supply voltage of the entire system including the flash memory, which poses a problem of erroneous operations of other chips such as a microprocessor in the system.
(2) Some flash memories have a configuration in which a page size (or a block size) can be changed for various uses.
For example, when the flash memory is used in the system requiring high-speed writing, erasing and reading, the page size of the flash memory is increased.
However, the large page size of the flash memory means a high load capacity generated in one bit line.
Therefore, the amount of current consumed at the start of writing, erasing and reading increases, and the peak current value also increases. As described above, the peak current causes a decrease in the value of the power supply voltage of the entire system including the flash memory, leading to the erroneous operations of other chips such as the microprocessor in the system.
On the other hand, when the page size of the flash memory is reduced, the load capacity generated in one bit line is decreased, so that problems such as a decrease in the power supply voltage hardly occur.
However, the reduced page size means a smaller number of bit lines in which writing, erasing and reading can be performed at a time, which is a disadvantage for a high-speed operation as far as the entire system is concerned.